The present application relates generally to methods for forming semiconductor devices, and more specifically to methods for forming fin field effect transistors (FinFETs) having a reduced risk of electrical shorts between gate and source/drain contacts.
A trend in the development of semiconductor manufacturing technologies has been to increase the density of devices per chip, and hence decrease the size of active structures as well as the distances between such structures. An increase in device density may advantageously affect device performance such as circuit speed, and may allow also for increasingly complex designs and functionality. However, the decrease in size and the attendant increase in density may also generate undesirable effects, including unwanted short circuits between adjacent conductive elements.
In advanced node FinFET devices, for instance, the proximity of gate contacts and source/drain contacts may lead to unwanted parasitic capacitance or conduction, i.e., leakage, between these adjacent structures, particularly at the respective top and bottom portions of the structures, which can adversely affect yield.